Semiconductor memories, such as random access memories (RAMs) and read-only memories (ROMs), are typically designed to operate in response to input signals in either a synchronous (clocked) or an asynchronous (unclocked) manner. One type of integrated circuit which operates primarily on asynchronous signals is a static random-access memory (SRAM). An SRAM device is designed to receive data values at data input terminals, and to statically provide the data values to memory cells corresponding to the value of the address applied to the SRAM, without relying on a clock signal indicating that the value at its data input terminals is valid.
Many modern SRAMs now include edge transition detection (ETD) circuits and other timing and control circuits that provide the SRAM device with performance benefits of internal dynamic operation. An ETD circuit detects transitions within the device and generates internal signals or "pulses" responsive to detecting such transitions. The internally-generated ETD pulses are employed to initialize the SRAM for commencement of a memory read or write cycle.
For example, the use of an ETD circuit allows the SRAM circuit to perform certain internal operations, such as precharging bit lines or deselecting sense amplifiers, after detection of an input signal transition. Upon presentation of new set of data to the SRAM, the transitions at the data input terminal cause the ETD circuit to enable the necessary functions of the SRAM in order to write the new data values into the addressed memory cells. An example of an ETD circuit used in SRAMs is described in U.S. Pat. No. 5,124,584, issued on Jun. 23, 1993, assigned to SGS-Thomson Microelectronics and herein incorporated by reference.
Conventional ETD circuitry is not without its shortcomings. For instance, an ETD pulse generated by the ETD circuitry which is utilized to initialize an SRAM device may possess a pulsewidth which is drastically reduced and in some cases eliminated due to input glitches appearing on the data input bus. In addition, ETD circuitry is typically separate and distinct from data input buffer circuitry, thereby increasing silicon layout overhead.
Noise or other interference may appear on an input data bus coupled to an SRAM device which may unexpectantly place the input data bus in an undesirable logic state for a temporary period of time. A noise glitch appearing on an input data bus of a conventional SRAM device may propagate therein and cause the wrong data values to be stored in the SRAM device.
Accordingly, there is a need for a data input buffer device and method for an SRAM for preventing noise appearing on a data input bus from adversely effective data storage and for generating edge transition detection signals with little overhead.